A hardware based implementation of neural networks applied to visual pattern recognition
Recent developments in microelectronic technology has diverted the interest of researchers towards hardware implementations of neural networks. The study is directed towards building a simple, small-scale, and fully functional neural network system applied to visual pattern recognition. Processing e...
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| Main Authors: | , , , |
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| Format: | text |
| Language: | English |
| Published: |
Animo Repository
1995
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| Online Access: | https://animorepository.dlsu.edu.ph/etd_bachelors/16599 |
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| Institution: | De La Salle University |
| Language: | English |
| Summary: | Recent developments in microelectronic technology has diverted the interest of researchers towards hardware implementations of neural networks. The study is directed towards building a simple, small-scale, and fully functional neural network system applied to visual pattern recognition. Processing elements used in implementing the Kohonen algorithm were constructed using available chip components. The software acts as a stand-alone simulation and provides an interface to and from the hardware module and a standard digital computer. The quality of recognition achievable is proportional to the number of neurons and the size of the input channel. Because distance is a relative quantity, deviations due to noise and impedance are inconsequential. Proper normalization and interpretation od data re more significant than the actual values generated. Properly training a neural network to identify a particular set of patterns is a highly heuristic endeavor. Thus, optimizing a map for a specific application requires a thorough understanding of the model, extensive experimentation, and ample training time. Viable neural network solutions in hardware are an attainable reality. However, further study and refinements are still necessary. |
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