CMOS implementation of hysteretic controller fo a DC-to-DC buck converter using 0.35um library

• Main Authors: Dela Cruz, Arainne Grace O., Li, Charles C., Tomboc, Cris Edward S., Ty, John Kerwin
• Format: text
• Language: English
• Published: Animo Repository 2017
• Subjects: DC-to-DC converters; Electric current converters
• Online Access: https://animorepository.dlsu.edu.ph/etd_honors/398
• Institution: De La Salle University

Hsyteretic comparators employ positive feedback mechanism which would enable the system to constantly check whether the output exceeds the lower and upper threshold voltages. By applying this system to a DC to DC buck converter, the use of pulse width modulated (PWM) signals would not be necessary anymore. In this research, a 3.3V input was stepped down to a 1.5 output with a minimum current of 10mA. A start-up circuit using XOR and XNOR gates were used to provide initial pulses from 0us to 100us in order to ensure that the buck converter can initially charge up and provide a change in the negative input of the comparator. An op-amp based reference bandgap voltage was also included in the design and was placed at the positive input terminal of the comparator. Testing was done on all process corner libraries and the output showed consistency, having only minimal deviations. Temperature sweep from 25°C to 80°C, line regulation from 2.9V to 3.3V, and load regulation from 100 to 500 were also checked and gave positive results. The output for load regulation ranged from 1.5038V to 1.5903V for a 100 load, and a 1.5239V to 1.6204V for a 500 load. The output voltage of the buck converter ranged from 1.2V to 2V thereby producing an average of around 1.5V. Among the process corner libraries, slow-slow (SS) produce the highest output voltage whihc was 1.55V. The overall circuit was implemented using tanner, and the pre-layout and post-layout designs had a maximum percent difference of 3.5% for both the voltage and the current. The final layout has a size of 1499.05um x 1056.1 um.