FPGA-based multi-decision level PID controller for boost converter
With the increasing demand of DC-DC converters due to the booming industry of handheld devices such as laptops, cellular phones, audio and video players, and digital cameras, plenty of techniques is being developed to regulate the voltage of the converters. This study introduces a digital proportion...
Saved in:
| Main Author: | |
|---|---|
| Format: | text |
| Language: | English |
| Published: |
Animo Repository
2010
|
| Subjects: | |
| Online Access: | https://animorepository.dlsu.edu.ph/etd_masteral/6134 https://animorepository.dlsu.edu.ph/context/etd_masteral/article/13160/viewcontent/CDTG004805_P.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Institution: | De La Salle University |
| Language: | English |
| Summary: | With the increasing demand of DC-DC converters due to the booming industry of handheld devices such as laptops, cellular phones, audio and video players, and digital cameras, plenty of techniques is being developed to regulate the voltage of the converters. This study introduces a digital proportional-integral-derivative (PID) controller with different decision levels based on output voltage and current levels. The PID controller is realized in hardware description language (HDL), which is employed in Xilinx Spartan 3E FPGA platform, and prototyped to regulate the output voltage of a boost converter. The controller uses pulse width modulation (PWM) and pulse frequency modulation (PFM) depending on the load current. At high load current, the controller runs in PWM mode with fixed frequency of 20 kHz, while at low load current, it switches to PFM mode with constant pulse duration of 10 μs. The pulse width or pulse repetition time is calculated using incremental PID algorithm until the output voltage reaches the target window of output voltage level. Experimental results show good voltage regulation and efficiency. Also even with input and load disturbances, the controller exhibits acceptable performance in limiting output voltage fluctuations. In addition, the design has decent reliability. The design does not require high resolution analog-to-digital converter (ADC) for capturing the output voltage and load current, and has significant potential to be implemented in application specific integrated chips (ASIC) or any programmable digital devices. |
|---|