FPGA library based design of a hardware model for convolutional neural network with automated weight compression using K-means clustering

• Main Authors: Yap, Roderick, Giron, Goldwin, Lanto, Leonard Miguel, Garcia, Lorenzo, Sta. Maria, David, Materum, Lawrence
• Format: text
• Published: Animo Repository 2019
• Subjects: Field programmable gate arrays; Neural networks (Computer science); Data compression (Computer science); VHDL (Computer hardware description language); Electrical and Electronics
• Online Access: https://animorepository.dlsu.edu.ph/faculty_research/3014
• Institution: De La Salle University

In this paper, a design of a synthesizable hardware model for a Convolutional Neural Network (CNN) is presented. The hardware model is capable of self-training i.e. without the use of any external processors. It is trained to recognize four numerical digit images. Another hardware model is also desi...