VLSI Implementation of an Efficient Lossless EEG Compression Design for Wireless Body Area Network

• Main Authors: Chen, Chiung-An, Wu, Chen, Abu, Patricia Angela R, Chen, Shih-Lun
• Format: text
• Published: Archīum Ateneo 2018
• Subjects: EEG; lossless compression; VLSI architecture; wireless body area network; Computer Sciences
• Online Access: https://archium.ateneo.edu/discs-faculty-pubs/187; https://archium.ateneo.edu/cgi/viewcontent.cgi?article=1186&context=discs-faculty-pubs
• Institution: Ateneo De Manila University

Data transmission of electroencephalography (EEG) signals over Wireless Body Area Network (WBAN) is currently a widely used system that comes together with challenges in terms of efficiency and effectivity. In this study, an effective Very-Large-Scale Integration (VLSI) circuit design of lossless EEG compression circuit is proposed to increase both efficiency and effectivity of EEG signal transmission over WBAN. The proposed design was realized based on a novel lossless compression algorithm which consists of an adaptive fuzzy predictor, a voting-based scheme and a tri-stage entropy encoder. The tri-stage entropy encoder is composed of a two-stage Huffman and Golomb-Rice encoders with static coding table using basic comparator and multiplexer components. A pipelining technique was incorporated to enhance the performance of the proposed design. The proposed design was fabricated using a 0.18 μm CMOS technology containing 8405 gates with 2.58 mW simulated power consumption under an operating condition of 100 MHz clock speed. The CHB-MIT Scalp EEG Database was used to test the performance of the proposed technique in terms of compression rate which yielded an average value of 2.35 for 23 channels. Compared with previously proposed hardware-oriented lossless EEG compression designs, this work provided a 14.6% increase in compression rate with a 37.3% reduction in hardware cost while maintaining a low system complexity.