VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT

• Main Authors: Chen, Shih Lun, Chou, He Sheng, Ke, Shih Yao, Chen, Chiung An, Chen, Tsung Yi, Chan, Mei Ling, Abu, Patricia Angela R., Wang, Liang Hung, Li, Kuo Chen
• Format: text
• Published: Archīum Ateneo 2023
• Subjects: bit map; block truncation coding; color sampling; Golomb–Rice coding; image compression; image sensor; IoT; machine learning; YEF color space; Biomedical; Computer Engineering; Electrical and Computer Engineering; Engineering
• Online Access: https://archium.ateneo.edu/discs-faculty-pubs/402; https://drive.google.com/file/d/1vs1cTlEgyqs9NUhdeQVcigR_UJISMsex/view?usp=sharing
• Institution: Ateneo De Manila University

It has always been a major issue for a hospital to acquire real-time information about a patient in emergency situations. Because of this, this research presents a novel high-compression-ratio and real-time-process image compression very-large-scale integration (VLSI) design for image sensors in the Internet of Things (IoT). The design consists of a YEF transform, color sampling, block truncation coding (BTC), threshold optimization, sub-sampling, prediction, quantization, and Golomb–Rice coding. By using machine learning, different BTC parameters are trained to achieve the optimal solution given the parameters. Two optimal reconstruction values and bitmaps for each 4 × 4 block are achieved. An image is divided into 4 × 4 blocks by BTC for numerical conversion and removing inter-pixel redundancy. The sub-sampling, prediction, and quantization steps are performed to reduce redundant information. Finally, the value with a high probability will be coded using Golomb–Rice coding. The proposed algorithm has a higher compression ratio than traditional BTC-based image compression algorithms. Moreover, this research also proposes a real-time image compression chip design based on low-complexity and pipelined architecture by using TSMC 0.18 μm CMOS technology. The operating frequency of the chip can achieve 100 MHz. The core area and the number of logic gates are 598,880 μm2 and 56.3 K, respectively. In addition, this design achieves 50 frames per second, which is suitable for real-time CMOS image sensor compression.