Reduction integrated circuits (IC) test time through statistical set-up verifier (SSUV).

Reduction integrated circuits (IC) test time through statistical set-up verifier (SSUV).

ABSTRACT See Upload (MT ENGRNG 067 2020)

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Bibliographic Details
Main Author: Dimal, Reynilan L.
Format: Theses and Dissertations NonPeerReviewed
Language:English
English
Published: 2020
Subjects:
T Technology (General)
TA Engineering (General). Civil engineering (General)
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://thesis.dlsud.edu.ph/7101/1/MT%20ENGRNG%20067%202020_watermark.pdf
http://thesis.dlsud.edu.ph/7101/2/DimalR%20-%20Reduction%20of%20IC%20Test%20Time_protected.pdf
http://thesis.dlsud.edu.ph/7101/
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Institution: De La Salle University
Language: English
English

Internet

http://thesis.dlsud.edu.ph/7101/1/MT%20ENGRNG%20067%202020_watermark.pdf
http://thesis.dlsud.edu.ph/7101/2/DimalR%20-%20Reduction%20of%20IC%20Test%20Time_protected.pdf
http://thesis.dlsud.edu.ph/7101/

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