An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clo...

Full description

Saved in:
Bibliographic Details
Main Authors: Edward, Alexander, Chan, Pak Kwong
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2013
Subjects:
Online Access:https://hdl.handle.net/10356/102296
http://hdl.handle.net/10220/16511
Tags: Add Tag
No Tags, Be the first to tag this record!
Institution: Nanyang Technological University
Language: English
id sg-ntu-dr.10356-102296
record_format dspace
spelling sg-ntu-dr.10356-1022962020-03-07T14:00:28Z An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS Edward, Alexander Chan, Pak Kwong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process. Published Version 2013-10-16T04:03:48Z 2019-12-06T20:52:53Z 2013-10-16T04:03:48Z 2019-12-06T20:52:53Z 2012 2012 Journal Article Edward, A., & Chan, P. (2012). An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS. IEICE transactions on electronics, 95(4), 733-743. 0916-8524 https://hdl.handle.net/10356/102296 http://hdl.handle.net/10220/16511 10.1587/transele.E95.C.733 en IEICE transactions on electronics © 2012 The Institute of Electronic, Information and Communication Engineers. This paper was published in IEICE transactions on electronics and is made available as an electronic reprint (preprint) with permission of The Institute of Electronic, Information and Communication Engineers. The paper can be found at the following official DOI: [http://dx.doi.org/10.1587/transele.E95.C.733]. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Edward, Alexander
Chan, Pak Kwong
An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
description This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Edward, Alexander
Chan, Pak Kwong
format Article
author Edward, Alexander
Chan, Pak Kwong
author_sort Edward, Alexander
title An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
title_short An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
title_full An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
title_fullStr An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
title_full_unstemmed An ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm CMOS
title_sort ultra-low voltage analog front end for strain gauge sensory system application in 0.18µm cmos
publishDate 2013
url https://hdl.handle.net/10356/102296
http://hdl.handle.net/10220/16511
_version_ 1681046734470381568