3-D mesh-based optical network-on-chip for multiprocessor system-on-chip

• Main Authors: Ye, Yaoyao, Xu, Jiang, Huang, Baihan, Wu, Xiaowen, Zhang, Wei, Wang, Xuan, Nikdast, Mahdi, Wang, Zhehui, Liu, Weichen, Wang, Zhe
• Other Authors: School of Computer Engineering
• Format: Article
• Language: English
• Published: 2013
• Subjects: DRNTU::Engineering::Computer science and engineering::Information systems
• Online Access: https://hdl.handle.net/10356/102583; http://hdl.handle.net/10220/16527
• Institution: Nanyang Technological University

Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated technologies offer an opportunity to continue performance improvements with higher integration densities. In this paper, we present a 3-D mesh-based ONoC for MPSoCs, and new low-cost nonblocking 4 × 4, 5 × 5, 6 × 6, and 7 × 7 optical routers for dimension-order routing in the 3-D mesh-based ONoC. Besides, we propose an optimized floorplan for the 3-D mesh-based ONoC. The floorplan follows the regular 3-D mesh topology but implements all optical routers in a single optical layer. The floorplan is optimized to minimize the number of extra waveguide crossings caused when merging the 3-D ONoC to one optical layer. Based on a set of real applications and uniform traffic pattern, we develop a SystemC-based cycle-accurate NoC simulator and compare the 3-D mesh-based ONoC with the matched 2-D mesh-based ONoC and 2-D electronic NoC for performance and energy efficiency. Additionally, we quantitatively analyze thermal effects on the 3-D 8 × 8 × 2 mesh-based ONoC.