An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators
This paper presents an asynchronous sub-two-step circuit architecture to reduce the complexity and power consumption of internal analog-to-digital converter (quantizer) for Continuous-Time Sigma-Delta Modulator (CTSDM). By using the proposed new circuit topology, only 1/3 of comparators for a 5-...
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| Main Authors: | , , |
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| 其他作者: | |
| 格式: | Conference or Workshop Item |
| 語言: | English |
| 出版: |
2015
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/103213 http://hdl.handle.net/10220/25740 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | This paper presents an asynchronous sub-two-step
circuit architecture to reduce the complexity and power
consumption of internal analog-to-digital converter (quantizer) for
Continuous-Time Sigma-Delta Modulator (CTSDM). By using the
proposed new circuit topology, only 1/3 of comparators for a 5-bit
quantizer design are needed when compared with the conventional
flash based counterpart. The proposed quantizer has been
implemented and fabricated in a UMC 65-nm CMOS process. The
measured results have shown that the quantizer consumes 0.59 mW
at an operating frequency of 250 MS/s in a 1.2 V supply and
achieves 28.82 dB SNDR (4.5 ENOB) from the output spectrum. |
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