Design of frequency-interleaved ADC with mismatch compensation

• Main Authors: Qiu, L., Zheng, Y. J., Siek, L.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2014
• Subjects: DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/103234; http://hdl.handle.net/10220/19986
• Institution: Nanyang Technological University

A frequency-interleaving-based multichannel analogue-to-digitial converter (ADC) with mismatch compensation is presented, which is immune from the time skew problem that exist in the time-interleaved ADC. The channel mismatches, such as bandwidth mismatch, gain mismatch, offset mismatch and filter bank mismatch, are addressed and modelled in the reconstruction optimisation. A prototype of a four-channel 1 GS/s 12 bit frequency-interleaved ADC (FI-ADC) is designed to demonstrate the mismatch compensation. Simulation results show that the mismatches in the FI-ADC can be compensated effectively.