Early output quasi-delay-insensitive array multipliers

• Main Authors: Balasubramanian, Padmanabhan, Maskell, Douglas, Naayagi, R. T., Mastorakis, Nikos
• Other Authors: School of Computer Science and Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Arithmetic Circuits; Multiplier; DRNTU::Engineering::Computer science and engineering
• Online Access: https://hdl.handle.net/10356/104734; http://hdl.handle.net/10220/48623
• Institution: Nanyang Technological University

Multiplication is a widely used arithmetic operation in microprocessing and digital signal processing applications, and multiplication is realized using a multiplier. This article presents the quasi-delay-insensitive (QDI) early output versions of recently reported indicating asynchronous array multipliers. Delay-insensitive dual-rail encoding is used for data representation and processing, and 4-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols are used for data communication. Many QDI array multipliers were realized using a 32/28 nm complementary metal oxide semiconductor (CMOS) technology. Compared to the optimum indicating array multiplier, the proposed optimum early output array multiplier achieves a 6.2% reduction in cycle time and a 7.4% reduction in power-cycle time product (PCTP) with respect to RTZ handshaking, and a 7.6% reduction in cycle time and an 8.8% reduction in PCTP with respect to RTO handshaking without an increase in the area. The simulation results also convey that the RTO handshaking is preferable to the RTZ handshaking for the optimum implementation of QDI array multipliers.