Dataflow optimized overlays for FPGAs

Dataflow optimized overlays for FPGAs

Dataflow Coprocessor Overlay (DaCO) is an FPGA-tuned dataflow-driven overlay architecture that offers fine-grained parallelism capable of delivering speedups of up to 2.8x on sparse, irregular computations over competing architectures (e.g. modern microprocessors and existing dataflow overlays). DaC...

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Bibliographic Details
Main Author: Siddhartha
Other Authors: Arvind Easwaran
Format: Theses and Dissertations
Language:English
Published: 2019
Subjects:
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
Online Access:https://hdl.handle.net/10356/104891
http://hdl.handle.net/10220/47803
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Institution: Nanyang Technological University
Language: English

Internet

https://hdl.handle.net/10356/104891
http://hdl.handle.net/10220/47803

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