Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}

Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}

Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude sca...

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Main Authors: Tay, Thian Fatt, Chang, Chip-Hong, Low, Jeremy Yung Shern
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2015
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Online Access:https://hdl.handle.net/10356/105036
http://hdl.handle.net/10220/25187
http://dx.doi.org/10.1109/TVLSI.2012.2221752
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1050362019-12-06T21:44:52Z Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1} Tay, Thian Fatt Chang, Chip-Hong Low, Jeremy Yung Shern School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude scaling operation preceding it. In order to correct the incorrectly scaled negative integer in residue form, substantial hardware overheads have been incurred to detect the range of the residues upon magnitude scaling. In this brief, a fast and area efficient 2n signed integer RNS scaler for the moduli set {2n-1, 2n, 2n+1} is proposed. A complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. Compared with the latest signed integer RNS scalers of comparable dynamic ranges, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup, and 32.5% of total power reduction for n ranging from 5 to 8. Accepted version 2015-03-09T02:47:13Z 2019-12-06T21:44:52Z 2015-03-09T02:47:13Z 2019-12-06T21:44:52Z 2013 2013 Journal Article Tay, T. F., Chang, C.-H., & Low, J. Y. S. (2013). Efficient VLSI Implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}. IEEE transactions on very large scale integration (VLSI) systems, 21(10), 1936-1940. 1063-8210 https://hdl.handle.net/10356/105036 http://hdl.handle.net/10220/25187 http://dx.doi.org/10.1109/TVLSI.2012.2221752 168511 en IEEE transactions on very large scale integration (VLSI) systems © 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/TVLSI.2012.2221752]. 5 p. application/pdf
institution Nanyang Technological University
building NTU Library
country Singapore
collection DR-NTU
language English
topic DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Tay, Thian Fatt
Chang, Chip-Hong
Low, Jeremy Yung Shern
Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
description Scaling is a problematic operation in residue number system (RNS) but a necessary evil in implementing many digital signal processing algorithms for which RNS is particularly good. Existing signed integer RNS scalers entail a dedicated sign detection circuit, which is as complex as the magnitude scaling operation preceding it. In order to correct the incorrectly scaled negative integer in residue form, substantial hardware overheads have been incurred to detect the range of the residues upon magnitude scaling. In this brief, a fast and area efficient 2n signed integer RNS scaler for the moduli set {2n-1, 2n, 2n+1} is proposed. A complex sign detection circuit has been obviated and replaced by simple logic manipulation of some bit-level information of intermediate magnitude scaling results. Compared with the latest signed integer RNS scalers of comparable dynamic ranges, the proposed architecture achieves at least 21.6% of area saving, 28.8% of speedup, and 32.5% of total power reduction for n ranging from 5 to 8.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Tay, Thian Fatt
Chang, Chip-Hong
Low, Jeremy Yung Shern
format Article
author Tay, Thian Fatt
Chang, Chip-Hong
Low, Jeremy Yung Shern
author_sort Tay, Thian Fatt
title Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
title_short Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
title_full Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
title_fullStr Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
title_full_unstemmed Efficient VLSI implementation of 2^n scaling of signed integer in RNS {2^n-1, 2^n, 2^n+1}
title_sort efficient vlsi implementation of 2^n scaling of signed integer in rns {2^n-1, 2^n, 2^n+1}
publishDate 2015
url https://hdl.handle.net/10356/105036
http://hdl.handle.net/10220/25187
http://dx.doi.org/10.1109/TVLSI.2012.2221752
_version_ 1681040572583772160

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