Hardware Trojan detection with linear regression based gate-level characterization
Due to outsourcing of IC fabrication, chip supply contamination is a clear and present danger, of which hardware Trojans (HTs) pose the greatest threat. This paper reviews the limitation of existing gate level characterization approaches to HT detection and presents a new detection method with a fas...
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sg-ntu-dr.10356-1050382019-12-06T21:44:54Z Hardware Trojan detection with linear regression based gate-level characterization Zhang, Li Chang, Chip-Hong School of Electrical and Electronic Engineering 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Due to outsourcing of IC fabrication, chip supply contamination is a clear and present danger, of which hardware Trojans (HTs) pose the greatest threat. This paper reviews the limitation of existing gate level characterization approaches to HT detection and presents a new detection method with a faster estimation of gate scaling factors by solving the normal equation of linear regression model. The HT-infected circuit can be distinguished from the genuine circuit without the need for a golden reference chip by their discrepancies in the bias parameter of the linear regression and a subset of the accurately estimated scaling factors. It has high detection sensitivity as long as the Trojan-to-circuit gate count ratio exceeds 0.4%. Accepted version 2015-03-03T09:24:44Z 2019-12-06T21:44:54Z 2015-03-03T09:24:44Z 2019-12-06T21:44:54Z 2014 2014 Conference Paper Zhang, L., & Chang, C.-H. (2014). Hardware Trojan detection with linear regression based gate-level characterization. 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 256-259. https://hdl.handle.net/10356/105038 http://hdl.handle.net/10220/25169 http://dx.doi.org/10.1109/APCCAS.2014.7032768 183020 en © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/APCCAS.2014.7032768]. 4 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems Zhang, Li Chang, Chip-Hong Hardware Trojan detection with linear regression based gate-level characterization |
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Due to outsourcing of IC fabrication, chip supply contamination is a clear and present danger, of which hardware Trojans (HTs) pose the greatest threat. This paper reviews the limitation of existing gate level characterization approaches to HT detection and presents a new detection method with a faster estimation of gate scaling factors by solving the normal equation of linear regression model. The HT-infected circuit can be distinguished from the genuine circuit without the need for a golden reference chip by their discrepancies in the bias parameter of the linear regression and a subset of the accurately estimated scaling factors. It has high detection sensitivity as long as the Trojan-to-circuit gate count ratio exceeds 0.4%. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Zhang, Li Chang, Chip-Hong |
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Conference or Workshop Item |
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Zhang, Li Chang, Chip-Hong |
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Zhang, Li |
title |
Hardware Trojan detection with linear regression based gate-level characterization |
title_short |
Hardware Trojan detection with linear regression based gate-level characterization |
title_full |
Hardware Trojan detection with linear regression based gate-level characterization |
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Hardware Trojan detection with linear regression based gate-level characterization |
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Hardware Trojan detection with linear regression based gate-level characterization |
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hardware trojan detection with linear regression based gate-level characterization |
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2015 |
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https://hdl.handle.net/10356/105038 http://hdl.handle.net/10220/25169 http://dx.doi.org/10.1109/APCCAS.2014.7032768 |
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