Tap delay-and-accumulate cost aware coefficient synthesis algorithm for the design of area-power efficient fir filters

• Main Authors: Qiao, Rui, Faust, Mathias, Chen, Jiajia, Chang, Chip-Hong, Ding, Jiatao
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: Structural Adder; FIR Filter Design; DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/105545; http://hdl.handle.net/10220/47824; http://dx.doi.org/10.1109/TCSI.2017.2725916
• Institution: Nanyang Technological University

Finite impulse response filters are widely used in digital signal processing applications. Prodigious research in the past two decades has substantially reduced the implementation cost of the multiple constant multiplication block. Further area and power consumption savings are stagnated by the structural adders and registers in the tap delay-and-accumulate line, which unfortunately dominate the overall hardware cost of FIR filter and are difficult to minimize by existing resource sharing approaches. Retiming or relocating the structural adders and registers can improve merely the throughput. To close the area-power efficiency gap, we reformulate the filter coefficient synthesis problem to explore the design space for the tap delay-and accumulate line by bisecting at some tap position. An efficient Genetic Algorithm is proposed to solve this integer programming problem at quadratic computational complexity by refining the search space for finding an optimized solution to fulfill the frequency response specifications. FPGA and ASIC logic synthesis results from twelve benchmark filter specifications showed that the average area and power consumptions of the solutions generated by our proposed algorithm have been reduced by up to 26.8% and 27.5% respectively, in comparison with the solutions obtained by existing design methods.