Near-threshold processor design techniques for power-constrained computing devices
Ultra-low power digital processors are needed in power-constrained computing devices for IoT, intelligent sensing and wearable computing applications. While near-threshold design is promising to achieve ultra-low power consumption, there are several challenges for this technology to be applied to th...
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sg-ntu-dr.10356-1058132019-12-06T21:58:27Z Near-threshold processor design techniques for power-constrained computing devices Zhou, Jun Kim, Tony Tae-Hyoung Lian, Yong School of Electrical and Electronic Engineering 2017 IEEE 12th International Conference on ASIC (ASICON) Near-threshold Processor DRNTU::Engineering::Electrical and electronic engineering Ultra-low Power Ultra-low power digital processors are needed in power-constrained computing devices for IoT, intelligent sensing and wearable computing applications. While near-threshold design is promising to achieve ultra-low power consumption, there are several challenges for this technology to be applied to the design of digital processors, including the functionality issue, performance degradation and variability issue. This paper reviews the existing near-threshold processor design techniques including circuit and architecture level solutions and discuss how the aforementioned issues can be addressed. Accepted version 2019-06-14T06:05:04Z 2019-12-06T21:58:27Z 2019-06-14T06:05:04Z 2019-12-06T21:58:27Z 2017 Conference Paper Zhou, J., Kim, T. T.-H., & Lian, Y. (2017). Near-threshold processor design techniques for power-constrained computing devices. 2017 IEEE 12th International Conference on ASIC (ASICON), 920-923. doi:10.1109/ASICON.2017.8252627 https://hdl.handle.net/10356/105813 http://hdl.handle.net/10220/48762 http://dx.doi.org/10.1109/ASICON.2017.8252627 en © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/ASICON.2017.8252627 4 p. application/pdf |
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Near-threshold Processor DRNTU::Engineering::Electrical and electronic engineering Ultra-low Power |
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Near-threshold Processor DRNTU::Engineering::Electrical and electronic engineering Ultra-low Power Zhou, Jun Kim, Tony Tae-Hyoung Lian, Yong Near-threshold processor design techniques for power-constrained computing devices |
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Ultra-low power digital processors are needed in power-constrained computing devices for IoT, intelligent sensing and wearable computing applications. While near-threshold design is promising to achieve ultra-low power consumption, there are several challenges for this technology to be applied to the design of digital processors, including the functionality issue, performance degradation and variability issue. This paper reviews the existing near-threshold processor design techniques including circuit and architecture level solutions and discuss how the aforementioned issues can be addressed. |
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School of Electrical and Electronic Engineering |
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School of Electrical and Electronic Engineering Zhou, Jun Kim, Tony Tae-Hyoung Lian, Yong |
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Conference or Workshop Item |
author |
Zhou, Jun Kim, Tony Tae-Hyoung Lian, Yong |
author_sort |
Zhou, Jun |
title |
Near-threshold processor design techniques for power-constrained computing devices |
title_short |
Near-threshold processor design techniques for power-constrained computing devices |
title_full |
Near-threshold processor design techniques for power-constrained computing devices |
title_fullStr |
Near-threshold processor design techniques for power-constrained computing devices |
title_full_unstemmed |
Near-threshold processor design techniques for power-constrained computing devices |
title_sort |
near-threshold processor design techniques for power-constrained computing devices |
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2019 |
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https://hdl.handle.net/10356/105813 http://hdl.handle.net/10220/48762 http://dx.doi.org/10.1109/ASICON.2017.8252627 |
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1681047199192973312 |