Area- and power-efficient nearly-linear phase response IIR filter by iterative convex optimization

• Main Authors: Deng, Gelei, Chen, Jiajia, Zhang, Jiaxuan, Chang, Chip-Hong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2019
• Subjects: IIR Filter Design; Digital IC Design; DRNTU::Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/106086; http://hdl.handle.net/10220/48873; http://dx.doi.org/10.1109/ACCESS.2019.2899107
• Institution: Nanyang Technological University

Low complexity infinite impulse response (IIR) filter design with nearly-linear phase response has attracted considerable attention in recent years due to the substantially high area and power consumption of linear phase finite impulse response (FIR) filter. Compared with the FIR filter, designing an IIR filter with the minimized group delay deviation and low power cost is a challenging topic. In this paper, the non-convex group delay deviation minimization problem for IIR filter design is reformulated into an iterative optimization problem to achieve lower group delay deviation. The hardware complexity of the solution is iteratively reduced by approximating the IIR filter coefficients to maximize the number of eliminable common subexpressions. The headroom for the coefficient adjustment is governed by the gradient of group delay deviation between iterations. Using our proposed design algorithm, a high-order lowpass filter with a minimum stopband attenuation of 60dB can be implemented by a 13-tap IIR filter with a group delay deviation of 0.002 only, as opposed to two linear-phase FIR filters designed by two recent and competitive FIR filter design algorithms with tap number of 51 and 57, respectively. Logic synthesis shows that the proposed IIR design saves 39.4% of the area and 41.8% of power consumption over the FIR solutions. Comparing with the latest nearly-linear phase IIR filter design algorithms, the group delay deviation of the solutions generated by our proposed algorithm are on average 25.5% lower, along with an average area and power savings of 20.5% and 18.4%, respectively, from the logic synthesis results.