Robust doublet STDP in a floating-gate synapse

• Main Authors: Gopalakrishnan, Roshan, Basu, Arindam
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2015
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
• Online Access: https://hdl.handle.net/10356/106928; http://hdl.handle.net/10220/25141; http://dx.doi.org/10.1109/IJCNN.2014.6889631
• Institution: Nanyang Technological University

Learning in a neural network typically happens with the modification or plasticity of synaptic weight. Thus the plasticity rule which modifies the synaptic strength based on the timing difference between the pre- and post-synaptic spike occurrence is termed as Spike Time Dependent Plasticity (STDP). This paper describes the neuromorphic VLSI implementation of a synapse utilizing a single floating-gate (FG) transistor that can be used to store a weight in a nonvolatile manner and demonstrate biological learning rules such as Long-Term Potentiation (LTP), Long-Term Depression (LTD) and STDP. The experimental STDP plot of a FG synapse (change in weight against Δt tpost tpre) from previous studies shows a depression instead of potentiation at some range of positive values of Δt for a wide set of parameters. In this paper, we present a simple solution based on changing control gate waveforms of the FG device that makes the weight change conform closely with biological observations over a wide range of parameters. We show results from a theoretical model to illustrate the effects of the modified waveform. The experimental results from a FG synapse fabricated in AMS 0.35μm CMOS process design are also presented to justify the claim.