Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications
In this paper, critical path of multiple constant multiplication (MCM) block is analyzed precisely and optimized for high-speed and low-complexity implementation. A delay model based on signal propagation path is proposed for more precise estimation of critical path delay of MCM blocks than the...
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sg-ntu-dr.10356-1073972019-12-06T22:30:07Z Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications Lou, Xin Yu, Ya Jun Meher, Pramod Kumar School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits In this paper, critical path of multiple constant multiplication (MCM) block is analyzed precisely and optimized for high-speed and low-complexity implementation. A delay model based on signal propagation path is proposed for more precise estimation of critical path delay of MCM blocks than the conventional adder depth and the number of cascaded full adders. A dual objective configuration optimization (DOCO) algorithm is developed to optimize the shift-add network configuration to derive high-speed and low-complexity implementation of the MCM block for a given fundamental set along with a corresponding additional fundamental set. A genetic algorithm (GA)-based technique is further proposed to search for optimum additional fundamentals. In the evolution process of GA, the DOCO is applied to each searched additional fundamental set to optimize the configuration of the corresponding shift-add network. Experimental results show that the proposed GAbased technique reduces the critical path delay, area, power consumption, area delay product and power delay product by 32.8%, 4.2%, 5.8%, 38.3% and 41.0%, respectively, over other existing optimization methods. Accepted version 2015-04-30T01:51:37Z 2019-12-06T22:30:07Z 2015-04-30T01:51:37Z 2019-12-06T22:30:07Z 2014 2014 Journal Article Lou, X., Yu, Y. J., & Meher, P. K. (2015). Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications. IEEE transactions on circuits and systems I : regular papers, 62(3), 863-872. https://hdl.handle.net/10356/107397 http://hdl.handle.net/10220/25477 http://dx.doi.org/10.1109/TCSI.2014.2377412 en IEEE transactions on circuits and systems I : regular papers © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [Article DOI: http://dx.doi.org/10.1109/TCSI.2014.2377412]. 13 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Lou, Xin Yu, Ya Jun Meher, Pramod Kumar Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
description |
In this paper, critical path of multiple constant
multiplication (MCM) block is analyzed precisely and optimized
for high-speed and low-complexity implementation. A delay
model based on signal propagation path is proposed for more
precise estimation of critical path delay of MCM blocks than
the conventional adder depth and the number of cascaded full
adders. A dual objective configuration optimization (DOCO)
algorithm is developed to optimize the shift-add network configuration
to derive high-speed and low-complexity implementation
of the MCM block for a given fundamental set along with a
corresponding additional fundamental set. A genetic algorithm
(GA)-based technique is further proposed to search for optimum
additional fundamentals. In the evolution process of GA, the
DOCO is applied to each searched additional fundamental set
to optimize the configuration of the corresponding shift-add
network. Experimental results show that the proposed GAbased
technique reduces the critical path delay, area, power
consumption, area delay product and power delay product by
32.8%, 4.2%, 5.8%, 38.3% and 41.0%, respectively, over other
existing optimization methods. |
author2 |
School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Lou, Xin Yu, Ya Jun Meher, Pramod Kumar |
format |
Article |
author |
Lou, Xin Yu, Ya Jun Meher, Pramod Kumar |
author_sort |
Lou, Xin |
title |
Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
title_short |
Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
title_full |
Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
title_fullStr |
Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
title_full_unstemmed |
Fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
title_sort |
fine-grained critical path analysis and optimization for area-time efficient realization of multiple constant multiplications |
publishDate |
2015 |
url |
https://hdl.handle.net/10356/107397 http://hdl.handle.net/10220/25477 http://dx.doi.org/10.1109/TCSI.2014.2377412 |
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1681035158954704896 |