Analysis and design of analogue class D amplifier output stages
It is well established that Class D audio amplifiers have higher power efficiency compared to classical linear amplifiers (Class A, Class B and Class AB) due to the fact that the transistors in their output stage operate either in the cut-off region or in the triode region. As the output stage typic...
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| 格式: | Theses and Dissertations |
| 語言: | English |
| 出版: |
2008
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| 主題: | |
| 在線閱讀: | https://hdl.handle.net/10356/13331 |
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| 機構: | Nanyang Technological University |
| 語言: | English |
| 總結: | It is well established that Class D audio amplifiers have higher power efficiency
compared to classical linear amplifiers (Class A, Class B and Class AB) due to the fact
that the transistors in their output stage operate either in the cut-off region or in the triode
region. As the output stage typically dissipates the highest power of all circuit blocks in
audio amplifiers, the overall power efficiency of amplifiers largely depends on the design
of the output stage.
The optimization of the output stage based on CMOS (embodying the p-channel-cum-nchannel
inverter) has been reported in literature. These output stages are limited only to
low voltage (~5V) applications due to the low breakdown voltage of CMOS. In this
dissertation, we investigate the power dissipation mechanisms of the High Voltage MOS
(HVMOS) output stage in half bridge configuration (the half bridge can be easily
extended to the full bridge) and the Double-diffused MOS (DMOS) output stage in full
bridge configuration, and apply protection circuits to the output stages for higher voltage
(~20V) applications. We derive analytical expressions to determine their power
efficiencies and establish a methodology to optimize the channel width of the output
stages for optimum power efficiency. We also propose a small non-overlapping logic
circuit to reduce the possibility of short-circuit current.
The derived expressions depict the parameters that affect power efficiency, and are
insightful to designers to design the output stage for optimum power efficiency in view of
IC area. The analytical results are verified against Cadence (Spectre) computer
simulations for both DMOS and HVMOS, and on the basis of measurements on an IC for
DMOS. The DMOS output stage is shown to offer higher power efficiency than the
HVMOS output stage due to its lower on-resistance and lower capacitance. |
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