I/O buffer model development from IBIS and IMIC for simulation in SPICE

• المؤلف الرئيسي: Wang, Ying.
• مؤلفون آخرون: Tan, Han Ngee
• التنسيق: Theses and Dissertations
• اللغة: English
• منشور في: 2008
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits; DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/13350

In today's high-speed and high IC density digital system, many new problems have appeared. One significant issue is signal integrity (SI) which concerns signal purity. Signal noise and signal delay due to interconnect have been becoming to dominate circuit performance. In order to design reliable digital circuits, SI analysis becomes imperative.