I/O buffer model development from IBIS and IMIC for simulation in SPICE

In today's high-speed and high IC density digital system, many new problems have appeared. One significant issue is signal integrity (SI) which concerns signal purity. Signal noise and signal delay due to interconnect have been becoming to dominate circuit performance. In order to design reliab...

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Main Author:	Wang, Ying.
Other Authors:	Tan, Han Ngee
Format:	Theses and Dissertations
Language:	English
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling
Online Access:	http://hdl.handle.net/10356/13350
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Institution:	Nanyang Technological University
Language:	English

id	sg-ntu-dr.10356-13350
record_format	dspace
spelling	sg-ntu-dr.10356-133502023-07-04T15:29:48Z I/O buffer model development from IBIS and IMIC for simulation in SPICE Wang, Ying. Tan, Han Ngee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling In today's high-speed and high IC density digital system, many new problems have appeared. One significant issue is signal integrity (SI) which concerns signal purity. Signal noise and signal delay due to interconnect have been becoming to dominate circuit performance. In order to design reliable digital circuits, SI analysis becomes imperative. Master of Engineering 2008-08-21T08:52:33Z 2008-10-20T07:26:03Z 2008-08-21T08:52:33Z 2008-10-20T07:26:03Z 1999 1999 Thesis http://hdl.handle.net/10356/13350 en 162 p. application/pdf
institution	Nanyang Technological University
building	NTU Library
continent	Asia
country	Singapore Singapore
content_provider	NTU Library
collection	DR-NTU
language	English
topic	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling
spellingShingle	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits DRNTU::Engineering::Computer science and engineering::Computing methodologies::Simulation and modeling Wang, Ying. I/O buffer model development from IBIS and IMIC for simulation in SPICE
description	In today's high-speed and high IC density digital system, many new problems have appeared. One significant issue is signal integrity (SI) which concerns signal purity. Signal noise and signal delay due to interconnect have been becoming to dominate circuit performance. In order to design reliable digital circuits, SI analysis becomes imperative.
author2	Tan, Han Ngee
author_facet	Tan, Han Ngee Wang, Ying.
format	Theses and Dissertations
author	Wang, Ying.
author_sort	Wang, Ying.
title	I/O buffer model development from IBIS and IMIC for simulation in SPICE
title_short	I/O buffer model development from IBIS and IMIC for simulation in SPICE
title_full	I/O buffer model development from IBIS and IMIC for simulation in SPICE
title_fullStr	I/O buffer model development from IBIS and IMIC for simulation in SPICE
title_full_unstemmed	I/O buffer model development from IBIS and IMIC for simulation in SPICE
title_sort	i/o buffer model development from ibis and imic for simulation in spice
publishDate	2008
url	http://hdl.handle.net/10356/13350
_version_	1772827165295902720

I/O buffer model development from IBIS and IMIC for simulation in SPICE

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