8-bit asynchronous dynamic reference analog-to-digital converter design

• Main Author: Adhika, Joseph Taruna
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Electronic circuits
• Online Access: https://hdl.handle.net/10356/139056
• Institution: Nanyang Technological University

In this project, an 8-bit asynchronous dynamic reference analog to digital converter (ADC) is designed using an 1.8V supply voltage and the CSM 0.18 µm CMOS technology.The ADC converts a sampled input signal into an 8-bit discrete digital output. Logic level "1" is represented by the supply voltage value 1.8 V and logic level "0" by 0 V. The circuit is designed using the Cadence®Virtuoso®Schematic Editor and simulated using the Cadence®Virtuoso®Analog Design Environment (ADE)-L. Additional ADC characterization is done using MATLAB®. The design consists of a wide-swing transconductance biasing circuit, ground compatible comparators, and R-2R Digital to Analog Converters (DAC). This project also utilizes Verilog-A modules, namely an ideal S/H circuit, ideal D-flip flops (DFF) and an ideal 8 bit DAC. The input range of the ADC is 0-1 V with a maximum sampling rate of 3.1 MSPS. At sampling frequency of 2 MHz, the proposed ADC managed to attain an SNR of 49.4582 dB, SINAD 49.4134 dB, SFDR 62.6466 dB, THD -62.5171 dB, and ENOB of 7.915 dB. Regarding non-linearity, the DNL of the ADC is 0.1534 and INL is 0.1433.