Design of a low power low drop-out regulator for wireless sensor nodes design project proposal

• Main Author: Koh, Su En
• Other Authors: Siek Liter
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/139917
• Institution: Nanyang Technological University

This project presents a design for a Low Drop-Out (LDO) Voltage Regulator, for application in wireless sensor nodes. The LDO provides a stable output voltage that is independent of changes in supply voltage, load current and temperature. The LDO operates with most transistors in subthreshold region for low current consumption and does not contain any resistors for low chip area. All simulations are done in the Cadence Virtuoso environment, using the Global Foundries 0.18μm CMOS technology, with a supply voltage of 1V and output capacitor of 100pF. The first design focuses on reducing the chip area while the second design focuses on improving the performance of the LDO. The final design can operate with a minimum supply voltage of 0.84V, supplying 20.7μA to the circuit. This produces an output voltage of 0.825V for load current up to 20mA. The design boosts a good load regulation of 0.316mV/mA and temperature coefficient of 18.5ppm/°C with a load current of 1mA. The line regulation of the circuit is 18.7mV/V and has a power supply rejection ratio of 32dB up to 100Hz. The undershoot and overshoot voltage of the circuit is 20.8mV and 17.1mV respectively with recovery time of 40μs and 30μs.