Spintronics devices for neuromorphic computing

• Main Author: Tang, Shawn Zhen Kee
• Other Authors: S.N. Piramanayagam
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Science::Physics
• Online Access: https://hdl.handle.net/10356/139993
• Institution: Nanyang Technological University

The increasing trend in computer ownership and usage has been going on for many years due to their processing power, competitive pricing and in some cases, portability. Majority if these computers use the classic von Neumann architecture in their design and their scalability and processing speeds have been accelerated thanks to Moore’s Law. However, Moore’s Law is expected to stagnate in the coming years and the von Neumann architecture is no longer considered to be power efficient as it was due to the segregation of processor and memory units creating bottlenecks and energy wastage. The alternative method is to implement a neuromorphic architecture, based on the human brain, that has the memory and processor units in the same compartment. This will improve scalability, clocking speeds and also power consumption. To implement this, we will need to have a memory unit that allows for quick data access and also allow multi-bit inputs and retention. In short, the processors will act as the neurons, and the memory devices as the synapses. Magneto-resistive random-access memory (MRAM) is seen as the future of RAM technology due to its non-volatility and lower power consumption. However, it is still not replicate the analogous memory of the synapse. To solve this, we discuss the possibility of using a geometrically pinned magnetic domain wall memory device that utilises anti-notches for pinning, as the free layer of an MTJ, for future use in a three-terminal MRAM. Although the final part of the experiment was not completed, the preparation and experimental methods have still been described to allow for reproducibility and completeness.