Design of FPGA based testing platform for modern memory

• Main Author: Li, Zehao
• Other Authors: Chang Chip Hong
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/140175
• Institution: Nanyang Technological University

With the wide application of FPGA in communication industry, the security of deployed hardware has been an important issue for the major vendors of FPGAs (i.e., Intel, Xilinx, Microsemi, etc.). It has been proved that the adversary is able to launch remote attacks such as fault or side-channel attacks to the different IP cores in an FPGA with hardware Trojans. In this report, a method of remote fault attack has been presented. It utilizes the existing loophole of dual port RAMs of an FPGA. With the opposite logic values write to same address simultaneously, the data stored in the bit cell will become undeterminable caused by transient short circuit of the back to back inverter. This phenomenon is called RAM collisions. If there are enough RAM collisions happening in a short time, there will be a serious voltage drop and heat generation of the FPGA board which may cause the bit-flip in the FPGA’s memory. The report describes the design, simulation and implementation of the RAM collision attack. The design components consist of a dual port ram module, two up and down counters, a PLL clock and an AES-128 encryption module. The AES-128 encryption is used to verify the bit-flip occurrence in the FPGA.