Digital timing mismatch detection and calibration for high-speed time interleaved ADC

• Main Author: Ho, Raymond
• Other Authors: Gwee Bah Hwee
• Format: Final Year Project
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering
• Online Access: https://hdl.handle.net/10356/140454
• Institution: Nanyang Technological University

High speed analog to digital converters (ADC) are required in high speed applications such as instrumentation applications, radar and communication systems, and consumer electronics. This project proposes techniques to achieve higher rates in analog to digital conversion using the available ADC. One way of improving the conversion frequency is by using interleaving technique which can be divided into time interleaving and frequency interleaving. The main problem in the state-of-the-art implementation of Time Interleaved ADC (TI-ADC) is the timing mismatch between the channels in the TI-ADC. An all-digital technique is proposed for calibrating the timing mismatch in TI-ADC. This technique consists of detection and correction algorithms. A novel and highly accurate Maximum Likelihood Timing Mismatch Detector (MLTMD) is proposed to find the mismatch values in all channels, whereas a Lagrange interpolating polynomial is used to compensate for the error introduced by the timing mismatch. Under an SNR of 83 dB in a 14-bit TI-ADC, the MLTMD is able to determine the mismatch at a resolution of better than 0.001% of the sampling period of the TI-ADC. A novel feature of the method proposed in this project is the combination of highly accurate detection and calibration methods which are independent of process, voltage and temperature variations. Numerical simulations have been done by using MATLAB, in order to give a proof-of-concept. This improvement is evaluated using standard ADC figures of merit such as Spurious Free Dynamic Range (SFDR) and Signal to Noise and Distortion Ratio (SNDR). Average SNDR and SFDR improvements of 45 dB and 58 dB across acquisition bandwidth at standard test conditions are able to be achieved. An alternative method to achieve high conversion rate using the concept of frequency interleaving is also proposed as an alternative and can be combined with the time interleaving method. Numerical simulation is also done for the Frequency Interleaved ADC (FI-ADC) and the advantages are discussed thoroughly.