Design of a low-voltage 40nm CMOS amplifier with high capacitive load

• Main Author: Sun, Jiayi
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/141321
• Institution: Nanyang Technological University

Nowadays, microelectronic products using batteries as power sources have been widely used. The exemplary applications such as internet-of-things and system-on-chips, which comprise large electronics systems, are the driving force for low-voltage low-power circuit design. This is mainly because low-voltage analog circuits are useful to reduce power consumption. Operational amplifier is a fundamental building block for use in analog or mixed-signal circuits. The design of low-voltage operational amplifier in advanced technology node is focused in this work. In this project, a low-voltage three-stage operational amplifier in 40nm CMOS technology is presented. The simulation results have shown that the amplifier has achieved a dc gain of 59.1dB, unity gain bandwidth of 1.15 MHz and a phase margin larger than 45° when driving a typical capacitive load of 150pF load at a minimum of 0.7V supply. When the capacitive load is increased to 500pF and 15nF respectively, the corresponding gain-bandwidth is obtained 0.37 MHz and 0.02 MHz. The performance benchmark comparison with the previously-reported works is conducted. Due to the improved frequency compensation technique, the proposed amplifier has exhibited better performance attributes in terms of small-signal and large-signal Figure-of-Merit (FoMs). The cornier simulation results have also revealed that the amplifier is stable against the process and temperature variations. The proposed amplifier will be useful for low-voltage signal processing applications in SoC or IoT.