Design and implementation of an array signal processing system
In this project, an array signal processing test-bed is constructed. This test-bed is named as the Versatile MIMO Antenna Processing System (vMAPS). vMAPs is a high-end data acquisition and processing system that combines the low cost and familiarity of a standard PC environment with high performanc...
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2008
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sg-ntu-dr.10356-141852023-03-04T03:21:01Z Design and implementation of an array signal processing system Ng, Boon Poh Feng, Aigang Lim, Khoon Seong Yang, Xuebin Bao, Haoji Hoay-Lim, Suat Geok Choo, Kien Huoy Mui, Eng Teck Wan, Yahong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing In this project, an array signal processing test-bed is constructed. This test-bed is named as the Versatile MIMO Antenna Processing System (vMAPS). vMAPs is a high-end data acquisition and processing system that combines the low cost and familiarity of a standard PC environment with high performance PCI products from Interactive Circuits and Systems Limited (ICS) and third party DSP and data storage hardware. The vMAPS uses WinNT, Windows 2000 or Windows 2000 server operating system and the popular LabView software for GUI based control and display. With the integration highly advanced PCI and PMC bus boards and associated software, a wide range of high speed and high accuracy data acquisition, storage, demodulation and sensor array processing applications can be easily configured. In the project, experiments are conducted on Direction of Arrival (DOA) estimation, adaptive beamforming and space-time coding. Experimental results show that the system is working satisfactory. 2008-11-06T02:34:29Z 2008-11-06T02:34:29Z 2007 2007 Research Report http://hdl.handle.net/10356/14185 en 139 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing Ng, Boon Poh Feng, Aigang Lim, Khoon Seong Yang, Xuebin Bao, Haoji Hoay-Lim, Suat Geok Choo, Kien Huoy Mui, Eng Teck Wan, Yahong Design and implementation of an array signal processing system |
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In this project, an array signal processing test-bed is constructed. This test-bed is named as the Versatile MIMO Antenna Processing System (vMAPS). vMAPs is a high-end data acquisition and processing system that combines the low cost and familiarity of a standard PC environment with high performance PCI products from Interactive Circuits and Systems Limited (ICS) and third party DSP and data storage hardware. The vMAPS uses WinNT, Windows 2000 or Windows 2000 server operating system and the popular LabView software for GUI based control and display. With the integration highly advanced PCI and PMC bus boards and associated software, a wide range of high speed and high accuracy data acquisition, storage, demodulation and sensor array processing applications can be easily configured. In the project, experiments are conducted on Direction of Arrival (DOA) estimation, adaptive beamforming and space-time coding. Experimental results show that the system is working satisfactory. |
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School of Electrical and Electronic Engineering |
author_facet |
School of Electrical and Electronic Engineering Ng, Boon Poh Feng, Aigang Lim, Khoon Seong Yang, Xuebin Bao, Haoji Hoay-Lim, Suat Geok Choo, Kien Huoy Mui, Eng Teck Wan, Yahong |
format |
Research Report |
author |
Ng, Boon Poh Feng, Aigang Lim, Khoon Seong Yang, Xuebin Bao, Haoji Hoay-Lim, Suat Geok Choo, Kien Huoy Mui, Eng Teck Wan, Yahong |
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Ng, Boon Poh |
title |
Design and implementation of an array signal processing system |
title_short |
Design and implementation of an array signal processing system |
title_full |
Design and implementation of an array signal processing system |
title_fullStr |
Design and implementation of an array signal processing system |
title_full_unstemmed |
Design and implementation of an array signal processing system |
title_sort |
design and implementation of an array signal processing system |
publishDate |
2008 |
url |
http://hdl.handle.net/10356/14185 |
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1759854508868894720 |