Development of electrical, electronic & information system

• Main Authors: Gwee, Bah Hwee., Sng, Kenneth Eng Kian., So, Ping Lam.
• Other Authors: School of Electrical and Electronic Engineering
• Format: Research Report
• Language: English
• Published: 2008
• Subjects: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
• Online Access: http://hdl.handle.net/10356/14242
• Institution: Nanyang Technological University

SOI technologies offer solutions to low power, high performance applications. The key device-architecture issue is the choice between partially depleted and fully depleted devices. While each structure has pros and cons, the choice needs to be balanced between process complexity and performance. Thereafter, engineers have ventured into some non-classical transistor structures will likely take over due to their delivery of higher performance with lower leakage than traditional scaled SOI CMOS approaches. The possibility of using a back gate have sparked a large research activity in the field of novel SOI devices. Among all other multiple gate design, it is well known that Gate-All-Around (GAA) MOSFET offers the most attractive properties for digital application. GAA MOSFET is being examined as extension of planar CMOS technology with potential to increase performance and packing density over the conventional technique.