A 40 GHz on-chip power combine load for mm-wave power amplifier

• Main Authors: Lin, Jiafu, Zhang, Gary, Boon, Chirn Chye
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2020
• 主題: Engineering::Electrical and electronic engineering; CMOS PA; Isolation
• 在線閱讀: https://hdl.handle.net/10356/144858
• 機構: Nanyang Technological University

Millimeter‐wave (Mm‐Wave) communication have been considered as one of the most potential candidate of the 5th generation communication (5G). However, the low breakdown voltage of CMOS challenges RF circuits design in various aspects especially for power amplifier (PA). The maximum available power from an unit transistor is limited by device characteristic thus power combining methods have been extensively investigated. This paper presents an on‐chip power combine load that can provide impedance transformation together with power combining for Mm‐Wave CMOS PA. A two‐way λ/6 power combine load has been implemented at 40 GHz on 0.18 µm CMOS technology, the measured return loss of each port is better than 15 dB and the loss is lower than 1.5 dB while isolation is better than 20 dB with a compact size (0.08 mm2).