A design methodology of transformer-based class-E power amplifier

• Main Author: Lim, Alfred Wee Chung
• Other Authors: Goh Wang Ling
• Format: Thesis-Doctor of Philosophy
• Language: English
• Published: Nanyang Technological University 2020
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/145281
• Institution: Nanyang Technological University

Wireless system has increasingly developing and growing since the first mobile phone systems was first introduced. Due to the technology advancement in CMOS process, it can provide a high level of integration, low-cost and the feasibility to operate at radio frequencies (RF) due to the significant scaling of the transistors, CMOS technology thus becomes the best solution in RF applications. However, this has also become a challenge in order to meet the requirements on efficiency, output power, linearity and bandwidth from a low voltage supply (VDD) arise from the scaling of transistors, especially the power amplifier (PA) one of the most important RF building blocks. For the PA, the efficiency is a big challenge for the overall performance of most wireless system. Therefore, the design of a high-efficiency PA is the . A power amplifier’s classes (A, AB, B, C, D, E, F, etc), and design fundamentals are presented. The class-E PA has a maximum theoretical efficiency of 100%. It consists of a single transistor that is driven as a switch and a passive load network. The passive load network is designed to minimize drain voltage and overlapping of current waveforms, which reduces the output power dissipation to the minimum. Of all the passive structures used in the class-E PA, high-quality inductors and transformers or baluns are the most difficult to realize monolithically due to their bigger size and loss as compared with other passive structures. In CMOS process they suffer from the presence of lossy substrates and high- resistivity metal, typically limiting the Q to about 7 to 10 at around 2 GHz. This causes many high-speed RF power PAs using on-chips inductors, to have limited performance compared to designs using off-chip components. However, the use of off-chip components adds complexity and cost to design of these circuits. In spite of its limitation, sub-micron CMOS prove to be the best process to implement the PA operating at frequency up to few GHz range. Therefore, the focus of this project is to propose a design methodology to improve the efficiency and output power of a class-E PA with on-chip transformer integrated in CMOS technology. Since the operation of the PA exerts a lot of stress on the switching transistor, a finite DC-feed inductance in the class-E load network is applied in order to reduce the drain-source voltage stress from 3.57 times to 2.5 times the supply voltage. Such an amplifier is designed and optimized by using an on-chip transformer such that the magnetic fluxes are constructive instead of destructive. Thus, the inductance reinforces itself and this reduces the sizes of both inductors significantly. Consequently, the quality factor of the on-chip inductors is enhanced and improve the efficiency due to lower inductor losses. The completed designs of the transformer-based class-E PA was submitted for fabrication using the GLOBALFOUNDRIES 65-nm RFCMOS technology is presented in chapter 3, 4 and 5 with different design techniques. The supply voltage of CMOS decreases with each new technology generation. To achieve sufficient output power at a low supply voltage, several design techniques have been proposed upon the use of on-chip transformer. The first approach is to use a transformation which makes the series resistance of the inductors smaller while still maintaining the inductance value. The second approach to use cascade or stacked transistor structure, which in combination with common-gate transistor allows operation at higher supply voltage while keeping reliability at a higher level. This result is higher output power, higher load and lower current, which potentially leads to lower losses and higher efficiency. The third approach to increase the output power for a given load is to use a differential structure. The signal is split into two anti-phase paths using a balun or transformer, two similar PA blocks are used, and the signal is merged at the PA output using the same technique. Simulated results were compared for the different approaches and contrasted against theoretical understanding using derived equations.