Quasi-delay-insensitive implementation of approximate addition

Asynchronous quasi-delay-insensitive (QDI) implementation of approximate addition is described in this article. The objective is to provide an insight into the optimization in design metrics that can be achieved with approximate addition compared to accurate addition based on a QDI implementation by...

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Main Authors: Balasubramanian, Padmanabhan, Mastorakis, Nikos E.
Other Authors: School of Computer Science and Engineering
Format: Article
Language:English
Published: 2021
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Online Access:https://hdl.handle.net/10356/145902
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Institution: Nanyang Technological University
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spelling sg-ntu-dr.10356-1459022021-01-14T02:02:44Z Quasi-delay-insensitive implementation of approximate addition Balasubramanian, Padmanabhan Mastorakis, Nikos E. School of Computer Science and Engineering Engineering::Computer science and engineering Approximate Addition Asynchronous Circuits Asynchronous quasi-delay-insensitive (QDI) implementation of approximate addition is described in this article. The objective is to provide an insight into the optimization in design metrics that can be achieved with approximate addition compared to accurate addition based on a QDI implementation by considering a practical digital image processing application. For the QDI implementation, some approximate adder architectures are considered which are deemed suitable for both ASIC and FPGA based implementations. The accurate and approximate adders considered are of size 32-bits. The delay-insensitive dual-rail code was used for data encoding, and four-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols were used separately for data communication. The implementations used a 32/28-nm complementary metal oxide semiconductor (CMOS) technology. The simulation results show that an approximate adder HOERAA achieves a 19.7% reduction in cycle time, a 12.5% reduction in area, and an 17.7% reduction in energy compared to the accurate adder for RTZ handshaking. For RTO handshaking, HOERAA achieves an 18.7% reduction in cycle time, a 12.4% reduction in area, and a 16.6% reduction in energy compared to the accurate adder. Another approximate adder HEAA achieves a 19.7% reduction in cycle time, a 12.9% reduction in area, and a 20.2% reduction in energy, compared to the accurate adder for RTZ handshaking. For RTO handshaking, HEAA achieves an 18.7% reduction in cycle time, a 12.9% reduction in area, and a 19.2% reduction in energy compared to the accurate adder. Nevertheless, the RTO handshaking is preferable to RTZ handshaking as the former facilitates slightly better optimizations in design metrics compared to the latter. The mean absolute error (MAE) and the root mean square error (RMSE), which are popular error metrics used in approximate computing, were calculated for the approximate adders and are given for a comparison. While the MAE of HOERAA and HEAA are comparable, HOERAA has 8.6% reduced RMSE compared to HEAA. Digital image processing results based on accurate and approximate additions are also given, to substantiate the usefulness of approximate addition. Published version 2021-01-14T02:02:43Z 2021-01-14T02:02:43Z 2020 Journal Article Balasubramanian, P., & Mastorakis, N. E. (2020). Quasi-delay-insensitive implementation of approximate addition. Symmetry, 12(11), 1919-. doi:10.3390/sym12111919 2073-8994 https://hdl.handle.net/10356/145902 10.3390/sym12111919 2-s2.0-85096601982 11 12 en Symmetry © 2020 The Authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Computer science and engineering
Approximate Addition
Asynchronous Circuits
spellingShingle Engineering::Computer science and engineering
Approximate Addition
Asynchronous Circuits
Balasubramanian, Padmanabhan
Mastorakis, Nikos E.
Quasi-delay-insensitive implementation of approximate addition
description Asynchronous quasi-delay-insensitive (QDI) implementation of approximate addition is described in this article. The objective is to provide an insight into the optimization in design metrics that can be achieved with approximate addition compared to accurate addition based on a QDI implementation by considering a practical digital image processing application. For the QDI implementation, some approximate adder architectures are considered which are deemed suitable for both ASIC and FPGA based implementations. The accurate and approximate adders considered are of size 32-bits. The delay-insensitive dual-rail code was used for data encoding, and four-phase return-to-zero (RTZ) and return-to-one (RTO) handshake protocols were used separately for data communication. The implementations used a 32/28-nm complementary metal oxide semiconductor (CMOS) technology. The simulation results show that an approximate adder HOERAA achieves a 19.7% reduction in cycle time, a 12.5% reduction in area, and an 17.7% reduction in energy compared to the accurate adder for RTZ handshaking. For RTO handshaking, HOERAA achieves an 18.7% reduction in cycle time, a 12.4% reduction in area, and a 16.6% reduction in energy compared to the accurate adder. Another approximate adder HEAA achieves a 19.7% reduction in cycle time, a 12.9% reduction in area, and a 20.2% reduction in energy, compared to the accurate adder for RTZ handshaking. For RTO handshaking, HEAA achieves an 18.7% reduction in cycle time, a 12.9% reduction in area, and a 19.2% reduction in energy compared to the accurate adder. Nevertheless, the RTO handshaking is preferable to RTZ handshaking as the former facilitates slightly better optimizations in design metrics compared to the latter. The mean absolute error (MAE) and the root mean square error (RMSE), which are popular error metrics used in approximate computing, were calculated for the approximate adders and are given for a comparison. While the MAE of HOERAA and HEAA are comparable, HOERAA has 8.6% reduced RMSE compared to HEAA. Digital image processing results based on accurate and approximate additions are also given, to substantiate the usefulness of approximate addition.
author2 School of Computer Science and Engineering
author_facet School of Computer Science and Engineering
Balasubramanian, Padmanabhan
Mastorakis, Nikos E.
format Article
author Balasubramanian, Padmanabhan
Mastorakis, Nikos E.
author_sort Balasubramanian, Padmanabhan
title Quasi-delay-insensitive implementation of approximate addition
title_short Quasi-delay-insensitive implementation of approximate addition
title_full Quasi-delay-insensitive implementation of approximate addition
title_fullStr Quasi-delay-insensitive implementation of approximate addition
title_full_unstemmed Quasi-delay-insensitive implementation of approximate addition
title_sort quasi-delay-insensitive implementation of approximate addition
publishDate 2021
url https://hdl.handle.net/10356/145902
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