Low power and high performance arithmetic circuit
This report presents several classes of XOR and Multiplexor based adders, 4-2 and 5-2 compressors are surveyed based on their delay, power and number of transistors for single unit block. The adders studied including the ripple carry adder, Carry select adder (CSA), Self Energy Recovery Full Adder a...
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sg-ntu-dr.10356-147402023-07-07T15:42:51Z Low power and high performance arithmetic circuit Hua, Ziyun. Lau Kim Teen School of Electrical and Electronic Engineering Centre for Integrated Circuits and Systems DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits This report presents several classes of XOR and Multiplexor based adders, 4-2 and 5-2 compressors are surveyed based on their delay, power and number of transistors for single unit block. The adders studied including the ripple carry adder, Carry select adder (CSA), Self Energy Recovery Full Adder and G-/P- XNOR based Full Adder. For the compressors, 7 XOR and 5 MUX modules forms nine 4-2 compressors and nine 5-2 compressors respectively. The delay, power will be tested under the worst case delay conditions. And the supply power ranged from 0.6 V to 3.3 V is examined to see the relationship to the performance. In the end, the transistors of each design will be countered. Bachelor of Engineering 2009-01-30T07:38:07Z 2009-01-30T07:38:07Z 2009 2009 Final Year Project (FYP) http://hdl.handle.net/10356/14740 en 79 p. application/pdf |
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DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Hua, Ziyun. Low power and high performance arithmetic circuit |
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This report presents several classes of XOR and Multiplexor based adders, 4-2 and 5-2 compressors are surveyed based on their delay, power and number of transistors for single unit block. The adders studied including the ripple carry adder, Carry select adder (CSA), Self Energy Recovery Full Adder and G-/P- XNOR based Full Adder. For the compressors, 7 XOR and 5 MUX modules forms nine 4-2 compressors and nine 5-2 compressors respectively. The delay, power will be tested under the worst case delay conditions. And the supply power ranged from 0.6 V to 3.3 V is examined to see the relationship to the performance. In the end, the transistors of each design will be countered. |
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Lau Kim Teen |
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Lau Kim Teen Hua, Ziyun. |
format |
Final Year Project |
author |
Hua, Ziyun. |
author_sort |
Hua, Ziyun. |
title |
Low power and high performance arithmetic circuit |
title_short |
Low power and high performance arithmetic circuit |
title_full |
Low power and high performance arithmetic circuit |
title_fullStr |
Low power and high performance arithmetic circuit |
title_full_unstemmed |
Low power and high performance arithmetic circuit |
title_sort |
low power and high performance arithmetic circuit |
publishDate |
2009 |
url |
http://hdl.handle.net/10356/14740 |
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1772828429960347648 |