Implementation of cache attacks in practical scenarios and toolkit development
The report describes the development of several software side-channel attacks which exploit cache vulnerabilities on Intel and ARM CPUs to break an AES (Advanced Encryption Standard) implementation. The cache vulnerabilities leak time-based information due to fetches from different areas of memor...
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sg-ntu-dr.10356-1480962021-04-23T13:09:37Z Implementation of cache attacks in practical scenarios and toolkit development Loh, Benjamin Wen Qian Li Fang School of Computer Science and Engineering Temasek Laboratories @ NTU Romain Poussier Thomas Peyrin ASFLi@ntu.edu.sg Engineering::Computer science and engineering The report describes the development of several software side-channel attacks which exploit cache vulnerabilities on Intel and ARM CPUs to break an AES (Advanced Encryption Standard) implementation. The cache vulnerabilities leak time-based information due to fetches from different areas of memory which can then be exploited to recover the full AES 128-bit keys. Theoretically, these side-channel attacks are easy to understand with existing literatures but are hard to implement in a practical scenario. In this project, the following side-channel attacks are developed: for Intel Central Processing Unit (CPU): (1) L1 Prime and Probe, (2) Last Level Core Prime and Probe, (3) Flush and Reload, (4) Evict and Reload and for ARM CPU: (5) Evict and Reload. These attacks are developed in C and illustrate a proof of concept of gathering the first nibble (i.e first 4 bits) of the AES key for each attack on an Ubuntu 18.04.3 LTS. Bachelor of Engineering (Computer Science) 2021-04-23T13:09:36Z 2021-04-23T13:09:36Z 2021 Final Year Project (FYP) Loh, B. W. Q. (2021). Implementation of cache attacks in practical scenarios and toolkit development. Final Year Project (FYP), Nanyang Technological University, Singapore. https://hdl.handle.net/10356/148096 https://hdl.handle.net/10356/148096 en SCSE20-0607 application/pdf Nanyang Technological University |
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Engineering::Computer science and engineering Loh, Benjamin Wen Qian Implementation of cache attacks in practical scenarios and toolkit development |
description |
The report describes the development of several software side-channel attacks which exploit
cache vulnerabilities on Intel and ARM CPUs to break an AES (Advanced Encryption Standard)
implementation. The cache vulnerabilities leak time-based information due to fetches from
different areas of memory which can then be exploited to recover the full AES 128-bit keys.
Theoretically, these side-channel attacks are easy to understand with existing literatures but are
hard to implement in a practical scenario. In this project, the following side-channel attacks are
developed: for Intel Central Processing Unit (CPU): (1) L1 Prime and Probe, (2) Last Level
Core Prime and Probe, (3) Flush and Reload, (4) Evict and Reload and for ARM CPU: (5)
Evict and Reload. These attacks are developed in C and illustrate a proof of concept of
gathering the first nibble (i.e first 4 bits) of the AES key for each attack on an Ubuntu 18.04.3
LTS. |
author2 |
Li Fang |
author_facet |
Li Fang Loh, Benjamin Wen Qian |
format |
Final Year Project |
author |
Loh, Benjamin Wen Qian |
author_sort |
Loh, Benjamin Wen Qian |
title |
Implementation of cache attacks in practical scenarios and toolkit development |
title_short |
Implementation of cache attacks in practical scenarios and toolkit development |
title_full |
Implementation of cache attacks in practical scenarios and toolkit development |
title_fullStr |
Implementation of cache attacks in practical scenarios and toolkit development |
title_full_unstemmed |
Implementation of cache attacks in practical scenarios and toolkit development |
title_sort |
implementation of cache attacks in practical scenarios and toolkit development |
publisher |
Nanyang Technological University |
publishDate |
2021 |
url |
https://hdl.handle.net/10356/148096 |
_version_ |
1698713689745522688 |