Circuit analysis for camouflage netlists

• 主要作者: Liu, YuCong
• 其他作者: Gwee Bah Hwee
• 格式: Final Year Project
• 語言: English
• 出版: Nanyang Technological University 2021
• 主題: Engineering::Electrical and electronic engineering
• 在線閱讀: https://hdl.handle.net/10356/148797
• 機構: Nanyang Technological University

The importance of intellectual property (IP) in Integrated Circuit (IC) design has steadily increased over the years as the demand for semiconductor ICs increased, especially after the global COVID-19 pandemic. Electronic Design Automation (EDA) tools have also become more powerful and easily available, enabling newer fab-less design houses to work independently to compete directly with the bigger players in the same market. This leads to stiff competition between design companies to compete for the best designs in a lucrative market. Traditionally, reverse engineering in IC design is used for verification purposes. However, malicious parties are now enabled with power tools such as advanced imagine equipment and techniques, Artificial Intelligence (AI) algorithms, and readily available EDA software to steal the IP from their competitors. The most straight-forward algorithm (Brute-force) is not very effective for reverse engineering as the common IC chips that we use consist of billions of transistor in one package. Thus, the brute-force attack is too long, making the mentioned algorithm not economically viable for the malicious party. However, as technology improves with faster processing ICs and an improvement in the brute-force algorithm, results show that there is still potential in this method of attacking camouflage circuits. In this project, a seven-functioned standard logic cell is proposed using the “Dummy Via” hardware obfuscation method and a python Verilog simulator is made to implement an effective brute-force algorithm to attack the camouflaged cell.