The design of CMOS-compatible plasmonic waveguides for intra-chip communication

• Main Authors: Liu, Yan, Ding, Lu, Cao, Yu, Wan, Dongyang, Yuan, Guanghui, Huang, Baohu, Thean, Aaron Voon-Yew, Mei, Ting, Venkatesan, Thirumalai, Nijhuis, Christian A., Chua, Soo-Jin
• Other Authors: School of Physical and Mathematical Sciences
• Format: Article
• Language: English
• Published: 2021
• Subjects: Science::Physics; CMOS-compatible Plasmonic Waveguide; Long-range SPP
• Online Access: https://hdl.handle.net/10356/149362
• Institution: Nanyang Technological University

A CMOS-compatible plasmonic waveguide with a metal or metal-like strip sandwiched in-between dielectrics has been proposed for intra-chip communication in the more-than-Moore era. A sequence of numerical models has been presented to evaluate the plasmonic waveguide performance. For device-level consideration, we demonstrated through simulations that Cu (1450 nm pitch) and PLD-TiN (900 nm pitch) plasmonic waveguides symmetrically sandwiched by SiO₂ with much smaller and hence denser interconnects,are promising candidates for use in global wires for the asynchronous communication. This design of plasmonic waveguide can bridge the CMOS circuitry and high-speed communication at optical frequencies within chip. For a system-level assessment, both of them have the same bandwidth throughput of∼19.8 Gbps. The other performance parameters of Cu and PLD-TiN plasmonic waveguides are respectively, signal latency of ∼0.18 ps and 0.19 ps,energy dissipation per computing bit of ∼2.5×10⁻³ fJ/bit and 3.8×10⁻³ fJ/bit, and 25% crosstalk coupling length of 155μm and 125μm. These findings suggest that plasmonic waveguide for intra-chip communication surpass those of existing electronic interconnects for all the categories of performance parameters.