Implementation and evaluation of AES algorithm

• 主要作者: Ren, Nan
• 其他作者: Gwee Bah Hwee
• 格式: Final Year Project
• 語言: English
• 出版: Nanyang Technological University 2021
• 主題: Engineering::Electrical and electronic engineering::Semiconductors
• 在線閱讀: https://hdl.handle.net/10356/149767
• 機構: Nanyang Technological University

As the information industry plays an increasingly important role in the national economy, the development of information technology and the security of data transmission has been attached importance to by the relevant departments. Encryption products to strengthen network information security have a wide range of application prospects. This topic mainly studies the principle and optimization of the AES encryption algorithm based on Verilog hardware description language, as well as the design of hardware implementation. This report first introduces the principle of the Advanced Encryption Algorithm (AES) and describes the similarities and differences between AES and Rijndael's design. Its features are security, high efficiency, easy expansion and optimization, and simple hardware realization. At the same time, this report also studies the key technology of algorithm realization. In the design process, the overall structure of the planning and the definition of each part of the port, the Verilog language to complete the description of the circuit Register-Transfer Level (RTL) level, at the same time using Mentor's ModelSim simulation tool for software platform simulation, to achieve the logic function of encryption and decryption of 128-bit key. The difference between synchronous AES encryption system and asynchronous AES system in design is analyzed. The defense of asynchronous AES against Side-Channel Attack (SNA) attack is also analyzed, which is mainly based on the physical signal changes of some circuits to prevent SNA. In contrast, the confidentiality of AES is improved, and optimization is achieved.