Design of a fast response CMOS low dropout regulator for system-on-chip applications

• Main Author: Wang, Haoran
• Other Authors: Chan Pak Kwong
• Format: Thesis-Master by Coursework
• Language: English
• Published: Nanyang Technological University 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits
• Online Access: https://hdl.handle.net/10356/150293
• Institution: Nanyang Technological University

Due to aggressive scaling-down of transistors for System-on-Chip (SoC) applications, there is an increasing demand of power management circuits and systems in industry. The Low-DropOut (LDO) regulator is regarded as one of the important building blocks in power management. It is widely utilized to supply function blocks which require good power efficiency and performance. In this work, a Flipped Voltage Follower (FVF) LDO regulator is proposed to achieve fast transient response. This regulator, which is designed with multiple feedbacks, is based on TSMC_40nm CMOS fabrication technology with 1V supply voltage and 0.8V output voltage. With 1ns rise/fall time, the settling time is obtained as 33.14ns. The overshoot and undershoot voltage spikes are 22.92mV and 38.70mV respectively at the 50mA step load current under a 100pF capacitive load. It has shown that the fast transient objective is met whilst both overshoot and undershoot are reasonably good. Finally, the stability analysis is conducted. The simulation result has illustrated that this LDO regulator is stable throughout the load current range. In comparison with reported works, the proposed work has shown improved transient metrics. Therefore, it is useful for SoC applications.