Partial order based non-preemptive communication scheduling towards real-time networks-on-chip
Due to the increasing performance requirement of cyberphysical systems, many-core processors with high parallelism are gaining wide utilization, where network-on-chip (NoC) is a prevalent choice for inter-core communication. Unfortunately, the contention on NoCs introduces large timing uncertainties...
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المؤلفون الرئيسيون: | , , , , , , , |
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مؤلفون آخرون: | |
التنسيق: | Conference or Workshop Item |
اللغة: | English |
منشور في: |
2021
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الموضوعات: | |
الوصول للمادة أونلاين: | https://hdl.handle.net/10356/151448 |
الوسوم: |
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المؤسسة: | Nanyang Technological University |
اللغة: | English |
الملخص: | Due to the increasing performance requirement of cyberphysical systems, many-core processors with high parallelism are gaining wide utilization, where network-on-chip (NoC) is a prevalent choice for inter-core communication. Unfortunately, the contention on NoCs introduces large timing uncertainties, which complicates the response time estimation. To address this problem, for real-time applications modeled as a directed acyclic graph (DAG), we introduce DAG-Order, a partial order based time-predictable scheduling paradigm, resulting in real-time NoCs. Specifically, DAG-Order is built upon an existing single-cycle long-range traversal (SLT) NoC
that is to simplify the process of validation and verification. Then, DAG-Order is proposed based on a dynamic scheduling approach, which jointly considers communication as well as computation workloads, and matches SLT NoC. DAGOrder achieves provably bound safety by enforcing certain partial order constraints among edges/vertices that eliminate the execution-timing anomaly during the runtime phase. Finally, an effective algorithm exploring for a proper schedule order is deployed to tighten the upper bound. Experimental results demonstrate that DAG-Order performs better than state-of-the-art scheduling approaches. |
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