A dual redundancy radiation-hardened flip-flop based on C-element in 65nm process

• Main Authors: Jaya, Gibran Limi, Chen, Shoushun, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Dual Redundancy Radiation-Hardened Flip-Fop; C-elements; Redundant Storage Elements; Single Upset Pulse
• Online Access: https://hdl.handle.net/10356/152168
• Institution: Nanyang Technological University

We propose a radiation-hardened flip-flop immune to the Single Event Upset (SEU) effect. Immunity was achieved through the use of C-elements and redundant storage elements. We take advantage of the property of C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the Flip-Flop. The Flip-Flop was implemented using 48 transistors and occupied an area of 30.78 um2, using 65nm CMOS process. It consumed 22.6% less transistors as compared to the traditional SEU resilient TMR Flip-flop.