Delayered IC image analysis with template‐based tanimoto convolution and morphological decision

Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques...

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Main Authors: Cheng, Deruo, Shi, Yiqiong, Lin, Tong, Gwee, Bah Hwee, Toh, Kar‐Ann
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2021
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Online Access:https://hdl.handle.net/10356/152375
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1523752021-12-11T20:12:00Z Delayered IC image analysis with template‐based tanimoto convolution and morphological decision Cheng, Deruo Shi, Yiqiong Lin, Tong Gwee, Bah Hwee Toh, Kar‐Ann School of Electrical and Electronic Engineering Engineering::Electrical and electronic engineering::Integrated circuits Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision Hardware Security Segmentation Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template-based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template-based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U-net while requiring 13× shorter training/validation time. To further improve the pixel-wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning-based TCMD-PL model. The proposed TCMD-PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling. Accepted version 2021-12-10T12:04:49Z 2021-12-10T12:04:49Z 2021 Journal Article Cheng, D., Shi, Y., Lin, T., Gwee, B. H. & Toh, K. (2021). Delayered IC image analysis with template‐based tanimoto convolution and morphological decision. IET Circuits, Devices & Systems. https://dx.doi.org/10.1049/cds2.12093 1751-858X https://hdl.handle.net/10356/152375 10.1049/cds2.12093 en IET Circuits, Devices & Systems © 2021 The Authors. IET Circuits, Devices & Systems published by John Wiley & Sons Ltd on behalf of The Institution of Engineering and Technology. This is an open access article under the terms of the Creative Commons Attribution-NonCommercial License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited and is not used for commercial purposes. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision
Hardware Security
Segmentation
spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
Engineering::Computer science and engineering::Computing methodologies::Image processing and computer vision
Hardware Security
Segmentation
Cheng, Deruo
Shi, Yiqiong
Lin, Tong
Gwee, Bah Hwee
Toh, Kar‐Ann
Delayered IC image analysis with template‐based tanimoto convolution and morphological decision
description Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template-based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template-based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U-net while requiring 13× shorter training/validation time. To further improve the pixel-wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning-based TCMD-PL model. The proposed TCMD-PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Cheng, Deruo
Shi, Yiqiong
Lin, Tong
Gwee, Bah Hwee
Toh, Kar‐Ann
format Article
author Cheng, Deruo
Shi, Yiqiong
Lin, Tong
Gwee, Bah Hwee
Toh, Kar‐Ann
author_sort Cheng, Deruo
title Delayered IC image analysis with template‐based tanimoto convolution and morphological decision
title_short Delayered IC image analysis with template‐based tanimoto convolution and morphological decision
title_full Delayered IC image analysis with template‐based tanimoto convolution and morphological decision
title_fullStr Delayered IC image analysis with template‐based tanimoto convolution and morphological decision
title_full_unstemmed Delayered IC image analysis with template‐based tanimoto convolution and morphological decision
title_sort delayered ic image analysis with template‐based tanimoto convolution and morphological decision
publishDate 2021
url https://hdl.handle.net/10356/152375
_version_ 1720447110173687808