Jo, Y., Kim, J. E., Baek, K., Kim, T. T., & Engineering, S. o. E. a. E. (2021). A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS.
Chicago Style CitationJo, Yong-Jun, Ju Eon Kim, Kwang-Hyun Baek, Tony Tae-Hyoung Kim, and School of Electrical and Electronic Engineering. A 0.007 Mm² 0.6 V 6 MS/s Low-power Double Rail-to-rail SAR ADC in 65-nm CMOS. 2021.
MLA引文Jo, Yong-Jun, et al. A 0.007 Mm² 0.6 V 6 MS/s Low-power Double Rail-to-rail SAR ADC in 65-nm CMOS. 2021.
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