A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS

• Main Authors: Jo, Yong-Jun, Kim, Ju Eon, Baek, Kwang-Hyun, Kim, Tony Tae-Hyoung
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering::Integrated circuits; SAR ADC; Compute-in-Memory
• Online Access: https://hdl.handle.net/10356/153185
• Institution: Nanyang Technological University

A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capac...