A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS

A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS

A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capac...

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Main Authors: Jo, Yong-Jun, Kim, Ju Eon, Baek, Kwang-Hyun, Kim, Tony Tae-Hyoung
Other Authors: School of Electrical and Electronic Engineering
Format: Article
Language:English
Published: 2021
Subjects:
Engineering::Electrical and electronic engineering::Integrated circuits
SAR ADC
Compute-in-Memory
Online Access:https://hdl.handle.net/10356/153185
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1531852023-04-18T01:16:37Z A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS Jo, Yong-Jun Kim, Ju Eon Baek, Kwang-Hyun Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering Chung-Ang University Centre for Integrated Circuits and Systems Engineering::Electrical and electronic engineering::Integrated circuits SAR ADC Compute-in-Memory A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step. 2021-11-15T00:57:11Z 2021-11-15T00:57:11Z 2021 Journal Article Jo, Y., Kim, J. E., Baek, K. & Kim, T. T. (2021). A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS. IEEE Transactions On Circuits and Systems II: Express Briefs, 68(9), 3088-3092. https://dx.doi.org/10.1109/TCSII.2021.3097126 1549-7747 https://hdl.handle.net/10356/153185 10.1109/TCSII.2021.3097126 9 68 3088 3092 en IEEE Transactions on Circuits and Systems II: Express Briefs © 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TCSII.2021.3097126. application/pdf
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering::Integrated circuits
SAR ADC
Compute-in-Memory
spellingShingle Engineering::Electrical and electronic engineering::Integrated circuits
SAR ADC
Compute-in-Memory
Jo, Yong-Jun
Kim, Ju Eon
Baek, Kwang-Hyun
Kim, Tony Tae-Hyoung
A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
description A 0.007mm 2 0.6V 6MS/s 10b double rail-to-rail input range SAR ADC is implemented in 65-nm technology. The extended input range broadens the applications of the low-power SAR ADCs such as compute-in-memory. The proposed ADC occupies less area since it only needs additional two series-connected capacitors and a differential-difference comparator for double rail-to-rail operation. The set-and-down operation reduces the input-referred noise of the comparator by over ten times than complementary switching. The novel metal-insulator-metal and metal-oxide-metal capacitor hybrid cap-DAC architecture minimize the gain error of ADC. The prototype achieves SNR of 53.90-dB, SNDR of 52.12-dB, and SFDR of 60.39-dB, power of 12.98- μW, and FoM of 6.6-fJ/conv.-step.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Jo, Yong-Jun
Kim, Ju Eon
Baek, Kwang-Hyun
Kim, Tony Tae-Hyoung
format Article
author Jo, Yong-Jun
Kim, Ju Eon
Baek, Kwang-Hyun
Kim, Tony Tae-Hyoung
author_sort Jo, Yong-Jun
title A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
title_short A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
title_full A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
title_fullStr A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
title_full_unstemmed A 0.007 mm² 0.6 V 6 MS/s low-power double rail-to-rail SAR ADC in 65-nm CMOS
title_sort 0.007 mm² 0.6 v 6 ms/s low-power double rail-to-rail sar adc in 65-nm cmos
publishDate 2021
url https://hdl.handle.net/10356/153185
_version_ 1764208043371790336

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