A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

• Main Authors: Kong, Junjie, Henzler, Stephan, Schmitt-Landsiedel, Doris, Siek, Liter
• Other Authors: School of Electrical and Electronic Engineering
• Format: Conference or Workshop Item
• Language: English
• Published: 2021
• Subjects: Engineering::Electrical and electronic engineering; Time-to-Digital Converter; Time-mode ADC; Body-biasing; Vernier TDC; Two-step Architecture
• Online Access: https://hdl.handle.net/10356/152172
• Institution: Nanyang Technological University

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, t...