A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC

This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, t...

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Main Authors: Kong, Junjie, Henzler, Stephan, Schmitt-Landsiedel, Doris, Siek, Liter
Other Authors: School of Electrical and Electronic Engineering
Format: Conference or Workshop Item
Language:English
Published: 2021
Subjects:
Engineering::Electrical and electronic engineering
Time-to-Digital Converter
Time-mode ADC
Body-biasing
Vernier TDC
Two-step Architecture
Online Access:https://hdl.handle.net/10356/152172
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Institution: Nanyang Technological University
Language: English
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spelling sg-ntu-dr.10356-1521722021-08-04T06:07:36Z A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC Kong, Junjie Henzler, Stephan Schmitt-Landsiedel, Doris Siek, Liter School of Electrical and Electronic Engineering 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering Time-to-Digital Converter Time-mode ADC Body-biasing Vernier TDC Two-step Architecture This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively. 2021-08-04T05:41:39Z 2021-08-04T05:41:39Z 2016 Conference Paper Kong, J., Henzler, S., Schmitt-Landsiedel, D. & Siek, L. (2016). A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 348-351. https://dx.doi.org/10.1109/APCCAS.2016.7803972 9781509015702 https://hdl.handle.net/10356/152172 10.1109/APCCAS.2016.7803972 2-s2.0-85011110684 348 351 en © 2016 IEEE. All rights reserved.
institution Nanyang Technological University
building NTU Library
continent Asia
country Singapore
Singapore
content_provider NTU Library
collection DR-NTU
language English
topic Engineering::Electrical and electronic engineering
Time-to-Digital Converter
Time-mode ADC
Body-biasing
Vernier TDC
Two-step Architecture
spellingShingle Engineering::Electrical and electronic engineering
Time-to-Digital Converter
Time-mode ADC
Body-biasing
Vernier TDC
Two-step Architecture
Kong, Junjie
Henzler, Stephan
Schmitt-Landsiedel, Doris
Siek, Liter
A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
description This paper presents the design of a 9-bit, Two-Step Time-to-Digital Converter (TDC) in 65 nm CMOS for the application in a time-mode ADC. The proposed TDC uses body-biasing in the fine TDC to obtain the resolution of the entire TDC, which is simulated to be 1.08 ps. With a dynamic range of 555 ps, the maximum conversion time between START and the availability of results is 2.7 ns. The proposed TDC consumes 0.667 mW at 200 MHz, with a FoM of 0.0065 pJ/conversion. The DNL and INL are simulated to be -0.097/0.2 LSB and -0.12/0.41 LSB respectively.
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Kong, Junjie
Henzler, Stephan
Schmitt-Landsiedel, Doris
Siek, Liter
format Conference or Workshop Item
author Kong, Junjie
Henzler, Stephan
Schmitt-Landsiedel, Doris
Siek, Liter
author_sort Kong, Junjie
title A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
title_short A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
title_full A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
title_fullStr A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
title_full_unstemmed A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC
title_sort 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm cmos for time-mode adc
publishDate 2021
url https://hdl.handle.net/10356/152172
_version_ 1707774604234194944

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