Circuit implementation of a four-dimensional topological insulator

• Main Authors: Wang, You, Price, Hannah M, Zhang, Baile, Chong, Yidong
• Other Authors: School of Physical and Mathematical Sciences
• Format: Article
• Language: English
• Published: 2021
• Subjects: Science::Physics; Topological Insulators; Quantum Hall
• Online Access: https://hdl.handle.net/10356/153344
• Institution: Nanyang Technological University

The classification of topological insulators predicts the existence of high-dimensional topological phases that cannot occur in real materials, as these are limited to three or fewer spatial dimensions. We use electric circuits to experimentally implement a four-dimensional (4D) topological lattice. The lattice dimensionality is established by circuit connections, and not by mapping to a lower-dimensional system. On the lattice's three-dimensional surface, we observe topological surface states that are associated with a nonzero second Chern number but vanishing first Chern numbers. The 4D lattice belongs to symmetry class AI, which refers to time-reversal-invariant and spinless systems with no special spatial symmetry. Class AI is topologically trivial in one to three spatial dimensions, so 4D is the lowest possible dimension for achieving a topological insulator in this class. This work paves the way to the use of electric circuits for exploring high-dimensional topological models.