A reference-sampling based calibration-free fractional-N PLL with a PI-linked sampling clock generator

• Main Authors: Han, Jae-Soub, Eom, Tae-Hyeok, Choi, Seong-Wook, Seong, Kiho, Yoon, Dong-Hyun, Kim, Tony Tae-Hyoung, Baek, Kwang-Hyun, Shim, Yong
• Other Authors: School of Electrical and Electronic Engineering
• Format: Article
• Language: English
• Published: 2022
• Subjects: Engineering::Electrical and electronic engineering; Calibration-Free; Fractional-N
• Online Access: https://hdl.handle.net/10356/153918
• Institution: Nanyang Technological University

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, -240.7 dB figure-of-merit (FoM), and -44.06 dBc fractional spurs with 8.17 mW power consumption.